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Professional Training |
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1. |
Cadence Voltage Storm PE |
6/05. |
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2. |
OEA Pplan/Pgrid |
7/02. |
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3. |
Synopsys Advanced Verilog |
6/00. |
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4. |
Synopsys Verilog Coding Styles
for RTL Synthesis |
5/00. |
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5. |
Synopsys Basic Verilog with VCS |
4/00. |
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6. |
Synopsys TimeMill/PowerMill |
3/00. |
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7. |
Motorola 1.8V, 0.2um
8Mb Late Write/DDR SRAM Circuit designer on loan to SRAM product team. Simulated sense amp enable time versus differential
bit line voltage across PVT corners for an adjustable delay circuit. Optimized sizing to minimize input control,
address, data, clock delays in frontend control block. Assisted in adding RC parasitics to spice macro model of 6T
SRAM. |
11/97 – 2/98. |
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8. |
Motorola University: CMOS
Circuit Design: Clocking |
10/97. |
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9. |
Motorola University: Perl
Programming |
6/97. |
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10. |
Motorola 2.7V,
0.5um Embedded 256KB 1T Flash
Memory Circuit Design Training for
6 months in High Density Flash Team. Generated 3D plots of p/n ratio, power, delay and
power-delay product using spice simulations of standard logic gates. Sized column decoder to optimize select and
deselect time of bitline with high voltage isolation transistor. Simulated
the effect of capacitive and current loading across PVT corners for an
unregulated negative charge pump in a triple-well process. |
3/96 – 9/96. |
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11. |
Motorola University: Memory
Design |
7/95. |
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12. |
IEEE Non-Volatile Semiconductor
Memory Workshop |
8/95. |
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