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2. |
Memory
Design and Project Management. |
10/96 – 5/03. |
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256KB
0.18um CMOS SRAM for Intel’s PXA27x. Project leader responsible for circuit
design and specification of a multi-vdd 64KB custom sram module. Supervised
layout, created verilog behavioral models,
generated modelsim patterns for fast spice functional verification and
power estimates. Using spice simulated race conditions and margin checks
across PVT corners and mentored junior engineers on team. Collaborated with backend integration, RTL
designers, custom analog designers and product engineers. |
7/00 – 5/03. |
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1Mb
0.25um 1.5T Embedded Flash Memory, Motorola. Project and Test Vehicle Characterization
Leader. Developed project plan, delegated design tasks in a team of 6
designers and documented post-silicon analog characterization
methodology. Simulated and verified
high voltage programming circuits and analog test modes for post-silicon
array characterization. Mentored junior engineers. Participated in bi-monthly
technology development planning, final mask data review with device
engineering and collaborated with product engineering. |
6/98 – 7/00. |
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256Kb 0.4um Embedded BST DRAM Test Vehicle,
Motorola. Technical leader responsible for circuit design, verification and
post-silicon characterization and test specification in a team of 3
engineers. Ran spice to characterize
timing and performed LVS. Collaborated with test engineer to debug test
vector timing for creating post-silicon bitmaps of write, read and refresh
timing. |
10/96 – 10/97. |
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