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Low
Power Systems Design, Integration and Validation |
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Power
Delivery Design and Verification, Intel. Led and
contributed to the power delivery and verification of the application
processors PXA3xx, PXA27x and PXA25x. Estimated chip power and used OEA’s
Pplan/Pgrid and spice to design and simulate multi-vdd power grids for
pre-layout specifications in 180nm, 90nm and 65nm projects. Managed 170GB of
project data to generate VoltageStorm simulations from lef, def, spef and
trans files for post-layout Cadence VoltageStorm simulations on second
silicon PXA3xx. Collaborated with Intel Design Automation to jointly validate
first silicon PXA3xx with AstroRail. Designed vdd power switches, modeled
power grid RC/gate loading and simulated power-on transient currents in
supplies using spice. Participated in cross-site sharing of design methods
and module re-use for the Communications Processor group. |
5/03 – 6/06. |
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SRAM Sneak Path Simulations for Idle/Low
Power Modes, Intel. Using ModelSim, Hsim and vtran, generated
patterns to examine sneak path currents across lvt, mvt and hvt multi-vdd
power domains in the 90nm PX3xx 768KB SRAM island. For the PXA27x, verified
power, firewall and level shifter functionality in idle, standby and sleep
modes using a post-layout Cap only extracted SRAM netlist. |
9/01 – 10/04. |
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Design for Manufacturability Analysis,
Intel. Using Hercules,
ran full-chip metal, poly, diffusion and via density checks on pre- and
post-dummified layout in the PXA3xx.
Reviewed min/max density error locations using Magma, Calibre and
Astro. Published problems for unit owners. Extracted node plots for top level
pre-tapeout power delivery validation in 180nm and 90nm designs. |
10/02 – 2/06. |
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Mixed-Signal Simulation and Validation, Intel. Performed ADVMS
simulations to compare Modelsim and Eldo results for the temperature sensor,
level-shifters, firewalls and pll in the PXA3xx. Identified the limitations of using
existing regression tests and spice scripts in this evaluation test of the
tool. |
7/04 – 10/04 |
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